The present invention relates generally to integrated circuit designs, and more particularly, to a system and method for dynamically managing power and frequency in an integrated circuit.
Battery-powered electronics systems continue to demand greater performance while strictly limiting the power consumption by device electronics, and particularly by their processors which consume the most power in the systems. Such battery-powered systems include laptop computers, personal digital assistants (PDAs), cell phones, and personal music and/or video players.
The performance of a processor is determined by the frequency of operation and the number of operations that can be completed on average per processor clock cycle. A dynamic power consumed in a CMOS transistor resulting from the switching of a load capacitance, CL, through a voltage, Vdd, at a clock frequency, f, is
  P  =            1      2        ⁢                  C        L            ·              V        dd        2            ·              f        .            Then dynamic power consumed in a chip is the sum of the power consumed by all its switching nodes. It can be modeled as the power of switching the average switching capacitance of the system, CSW, through the voltage, Vdd,
                    P        =                              1            2                    ⁢                                    C              SW                        ·                          V              dd              2                        ·            f                                              (        1        )            
Examination of Equation (1) shows that if a slight voltage dependence of the switching capacitance is ignored, the dynamic power consumption of a system is quadratically more sensitive to power-supply voltage than is the clock frequency. While clock frequency determines a system's performance, voltage is much more sensitive to power efficiency. When voltage supply to an integrated circuit is lowered, its operating frequency will be lowered as well. So in order to maintain a performance level, a certain clock frequency is required, then the system seeks a minimum voltage to maintain that clock frequency.
In some cases, different applications may have difference performance requirements. Using laptop computers as an example, the computational requirements can be considered to fall into one of three categories: compute-intensive, low-speed, and idle. Compute-intensive and short-latency tasks (e.g., video decompression, speech recognition, complex spreadsheet operations, etc.) utilize the full throughput of the processor. Low speed and long-latency tasks (e.g., text entry, address book browsing, playing music, etc.) only require a fraction of the full processor throughput to adequately run. Executing these tasks faster than the desired throughput rate has no discernible benefit. In addition, there are system idle periods because single-user systems are often not actively computing. A key design objective for the processor systems in these applications is to provide the highest possible peak throughput for the compute-intensive tasks while maximizing the battery life for the remaining low speed and idle periods.
A common power-saving technique is to reduce the clock frequency during non-compute-intensive activity. This reduces power, but does not affect the total energy consumed per task, since energy consumption is independent of clock frequency to a first order approximation. Intuitively, executing a task slower only takes longer time, and total energy consumption is still the same. Conversely, reducing the voltage of the processor improves its energy efficiency, but compromises its peak throughput. If, however, both clock frequency and supply voltage are dynamically varied in response to computational load demands, then the energy consumed per task can be reduced for the low computational periods, while retaining peak throughput when required. When a majority of the computation does not require maximum throughput, then the average energy consumption can be significantly reduced, thereby increasing the computation that can be done with the limited energy supply of a battery.
A prior art dynamic voltage and frequency management (DVFM) system employs dynamic frequency and voltage scaling separately. The dynamic frequency scaling module monitors activity levels of main logic circuits, and scales up the frequency when the circuit activity is high, and scales down the frequency when the circuit activity is low. After the frequency is determined, the separate dynamic voltage scaling module scales the supply voltage, i.e., increasing, decreasing or keeping the present supply voltage, based on delay information of the main logic circuits. There are drawbacks of this kind of DVFM system, such as its circuit is very complicated due to separate dynamic frequency and voltage scaling modules. It also cannot determine the lowest frequency the circuit can operate given a certain supply voltage.
As such, what is desired is a DVFM system that are easy to implement and can control voltage and frequency with greater flexibility.